1. Field of the Invention
The present invention relates to the formation of integrated circuits, and, more particularly, to the formation of field effect transistors having a channel region with a specified intrinsic stress to improve the charge carrier mobility.
2. Discussion of the Background
Integrated circuits are formed of a large number of individual circuit elements, such as transistors, capacitors, resistors, etc. These elements are connected internally to form complex circuits, such as memory devices, logic devices and microprocessors. The performance of integrated circuits can be improved by increasing the number of functional elements in the circuit in order to increase its functionality and/or by increasing the speed of operation of the circuit elements. A reduction of feature sizes allows the formation of a greater number of circuit elements on the same area, hence allowing an extension of the functionality of the circuit, and also reduces signal propagation delays, thus making an increase of the speed of operation of circuit elements possible.
Metal-oxide-semiconductor field-effect transistors (MOSFETs, or FETs) are used as switching elements in integrated circuits. FETs allow control of a current flowing through a channel region located between a source region and a drain region. The source region and the drain region are highly doped. In N-type transistors (or NFETs, or NMOSs), the source and drain regions are doped with an N-type dopant. Conversely, in P-type transistors (or PFETs, or PMOSs), the source and drain regions are doped with a P-type dopant. The doping of the channel region is inverse to the doping of the source region and the drain region. The conductivity of the channel region is controlled by a gate voltage applied to a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. Depending on the gate voltage, the channel region may be switched between a conductive “on” state and a substantially non-conductive “off” state.
When reducing the size of FETs, it is important to maintain a high conductivity of the channel region in the “on” state. The conductivity of the channel region in the “on” state depends on the dopant concentration in the channel region, the mobility of the charge carriers, the extension of the channel region in the width direction of the transistor and the distance between the source region and the drain region, which is commonly denoted as “channel length.” While a reduction of the width of the channel region leads to a decrease of the channel conductivity, a reduction of the channel length enhances the channel conductivity. However, further reduction of the channel length entails a plurality of obstacles associated therewith, for example, relating to the reliability and reproducibility of advanced techniques of photolithography and etching needed to create such transistors having short channel lengths.
In view of the problems associated with a further reduction of the channel length, it has been proposed to also enhance the performance of field effect transistors by increasing the charge carrier mobility in the channel region. One approach that may be used to increase the charge carrier mobility involves modifying the lattice structure in the channel region by creating tensile or compressive stress. This leads to a modified mobility of electrons and holes, respectively. A tensile stress in the channel region increases the mobility of electrons. When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress can enhance electron mobility (or n-channel FET drive currents), while compressive stress can enhance hole mobility (or p-channel FET drive currents).
Several methods of forming FETs having stressed channel regions have been proposed. In one such method, a layer including an alloy of silicon and germanium or an alloy of silicon and carbon, respectively, is introduced into (or below) the channel region in order to create a tensile or compressive stress, as discussed in U.S. Pat. No. 7,157,374 and U.S. Pub. No. 2007/0207583. In another such method, the stresses are placed on the channel regions through the use of intrinsically-stressed barrier dielectric layers (e.g., silicon nitride layers) formed over the transistors, as discussed in U.S. Pub. No. 2007/0007552 and U.S. Pub. No. 2007/0207583.
However, one problem typically associated with the implementation of such methods of forming field effect transistors having stressed channel regions is that the formation of the stress-creating structure requires considerable modification of conventional and well-approved techniques used for the formation of FETs. Thus, the complexity of the formation of the transistors is significantly increased compared to the formation of transistors without stress-creating structures. Thus, a need exists for a method allowing the creation of desired stress conditions in a FET without requiring substantial modifications to the manufacturing process.